An integrated circuit may contain metal oxide semiconductor (MOS) transistors with gate lengths less than 30 nanometers and gate pitch distances less than 100 nanometers. It may be desirable for some gates to have more narrow widths than other gates, for example in some logic circuits or in static random access memory (SRAM) cells. Lithography processes for forming the gates may use an illumination source, for example a 193 nanometer argon-fluoride excimer laser may be incapable of directly printing an etch mask for the gates at the desired pitch distances and widths. One approach to forming the etch mask for the gates is to perform two or more pattern steps, patterning a subset of the gates in each pattern step. Double or multiple patterning can print gates with two different widths, but extra patterning undesirably increases fabrication cost and process complexity of the integrated circuit. Another approach is to form a gate etch mask from a spacer layer deposited over mandrels. An etch mask for the mandrels for all the gates can be printed in one pattern step. However, gate lengths of the gate etch mask are determined by the thickness of the deposited spacer layer, and so forming gates with two different widths may be problematic. Similar limitations may be noted in regard to an integrated circuit containing fin field effect transistors (finFETs) with fins on pitch distances that are smaller than the single-pattern capability of the photolithographic process. Forming fins with two different fin widths may be problematic.